Staff PCIe Design Engineer
Core
Designing and integrating PCIe, CXL, and other I/O subsystems into System-on-Chips (SoCs) for compute platforms.
Role type
Staff IC digital hardware design engineer (SoC/I/O subsystems)
Builds
Complex compute subsystems and SoCs integrating PCIe, CXL, UCIe, and Ethernet
Domain
Semiconductor / Hardware Design
Required skills
Digital hardware design, Verilog HDL, SoC development, PCIe/CXL/UCIe/Ethernet integration, Static design checks (CDC/RDC/X-Propagation/Linting), Scripting (Perl/Python)
Preferred skills
ARM-based designs, Team leadership, Synthesis and timing analysis, Power management, DFT, Physical implementation
Technologies
Verilog, Perl, Python, PCIe, CXL, UCIe, Ethernet, RTL, SoC
Responsibilities
Write micro-architecture specifications and develop RTL, Collaborate on architecture review and build specifications, Debug design issues with verification team, Optimize system performance with analysis team, Assist with floor planning, constraints, and timing closure, Contribute to design methodologies, Guide and support team members
Seniority
Staff, hands-on IC with mentorship