Principal Digital Design Engineer (AI Fabric)
Core
Architect and implement next-generation digital designs for high-performance connectivity solutions, owning complex blocks from micro-architecture through silicon bring-up.
Role type
Principal Digital Design Engineer (SoC/Silicon)
Builds
High-performance connectivity solutions (CXL, Ethernet, NVLink, PCIe, UALink) for rack-scale AI infrastructure
Domain
Semiconductor hardware design, AI infrastructure, Server/Storage/Networking
Deliverable
production ML models | product features
Required skills
RTL coding, micro-architecture definition, timing closure, DFT implementation, advanced CMOS node design (≤7nm), high-speed protocol expertise (PCIe, Ethernet, Infiniband, DDR), UVM verification, Cadence/Synopsys flows, silicon bring-up and debug
Preferred skills
Embedded firmware collaboration, embedded processor subsystems (RISC-V, Arm), design methodology/CAD automation contributions
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, Cadence, Synopsys, UVM, GDS
Responsibilities
Define micro-architecture and drive digital design for complex blocks; collaborate with verification teams for test plans and coverage closure; lead timing closure and DFT implementation; facilitate silicon bring-up and debug; mentor junior engineers; drive designs to production ensuring quality and schedule
Seniority
Principal, hands-on IC with mentorship
