ASIC Design Engineer - Tel-Aviv Office
Core
Develop digital and mixed-signal blocks from specification through RTL implementation, focusing on power-efficient, implementation-aware design for advanced flash memory products.
Role type
Senior IC ASIC RTL design engineer
Builds
Advanced flash memory products (NAND/NOR)
Domain
Semiconductor / Memory Storage
Required skills
SystemVerilog, ASIC front-end flows, static timing analysis, UPF-based power intent, CDC/RDC analysis, PPA trade-offs, synthesis tools, simulation tools
Preferred skills
Design Compiler, PrimeTime, clock gating, power gating, multi-voltage designs, CMOS circuit concepts, memory architecture
Technologies
SystemVerilog, Design Compiler, PrimeTime, UPF
Responsibilities
Develop and implement RTL for digital and mixed-signal blocks; Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR; Design power- and area-efficient RTL; Complete RTL- and gate-level power and timing evaluation; Collaborate with verification, synthesis, and physical design teams.
Seniority
Senior, hands-on IC
