Senior Principal Engineer – Hardware Chip Lead, Connectivity BU
Core
Lead end-to-end hardware design and program delivery for advanced optical DSP ASICs serving hyperscale data center, enterprise, and AI infrastructure markets.
Role type
Senior Principal Hardware Chip Lead (IC)
Builds
Multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers for 100G+ per lane fiber optical networks.
Domain
Semiconductor / Optical Communications / High-Speed SerDes
Required skills
SoC/ASIC architecture, high-speed SerDes (100G+), mixed-signal design, advanced CMOS nodes (2nm/3nm/5nm), RTL, physical design, timing closure, silicon bring-up, ATE test program development, cross-functional team leadership
Preferred skills
Optical DSP/transceiver architectures, eAVS power optimization, Silicon Photonics (SiPho) integration, multi-site global engineering management
Technologies
TSMC 2nm/3nm/5nm, SerDes, DSP datapath, RTL, STA, ATE, HTOL, ESD, LU
Responsibilities
Own chip program from POR to MPR; define PRD and bring-up requirements; coordinate cross-functional teams (analog, digital, DV, PD, firmware, validation); lead silicon bring-up and validation; mentor engineering talent; drive resolution of post-silicon issues
Seniority
Principal, hands-on IC with program leadership
