Senior Principal Engineer – Hardware Chip Lead, Connectivity BU
Core
Lead end-to-end hardware design and program delivery for advanced optical DSP ASICs serving hyperscale data center, enterprise, and AI infrastructure markets.
Role type
Senior Principal Hardware Chip Lead (IC)
Builds
Multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers
Domain
Semiconductor / Optical Communications / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
SoC/ASIC architecture, high-speed SerDes (100G+/lane), mixed-signal design, advanced CMOS nodes (2nm/3nm/5nm), RTL design, physical design, DFT, STA, silicon bring-up, ATE test program development, cross-functional team leadership
Preferred skills
optical DSP, coherent/direct-detect transceiver architectures, high-speed retimer products, eAVS power optimization, SiPho integration
Technologies
TSMC 2nm/3nm/5nm, SerDes, RTL, DFT, STA, ATE
Responsibilities
Define product requirements and bring-up specs, represent hardware at program milestones, coordinate cross-functional teams, lead chip design execution from architecture to tape-out, manage silicon bring-up and validation, mentor engineering talent
Seniority
Principal, hands-on IC with strategic oversight