Senior/ Staff Physical Design Engineer
Core
Architecting the physical implementation of complex semiconductor chips for rack-scale AI infrastructure, transforming logic into high-performance silicon.
Role type
Senior/Staff Physical Design Engineer (Backend)
Builds
Custom connectivity solutions and standards-based chips for hyperscalers and AI clusters
Domain
Semiconductor / AI Infrastructure / High-speed connectivity
Deliverable
production ML models
Required skills
Physical Design flow (Synthesis, Floorplanning, Place & Route, CTS), Timing Signoff (STA), Physical Verification (DRC/LVS), Reliability analysis (EMIR), Logic Equivalence Checking (LEC), Advanced process nodes (7nm and below), Scripting (TCL/Python)
Preferred skills
Full-chip implementation, Power and Noise analysis (SI/PI), Design-for-Test (DFT), High-speed interface protocols
Technologies
Synopsys Fusion Compiler/ICC2, Cadence Innovus
Responsibilities
Establish local backend execution culture and technical standards in a new R&D center, own the full physical implementation journey from synthesis to signoff, drive design integrity through rigorous verification flows, define and refine backend methodologies with autonomy, collaborate with Architecture, Design, and DFT teams on advanced process nodes
Seniority
Senior/Staff, hands-on IC with strategic site-building impact
