Senior Physical Design Engineer
Core
Drive end-to-end execution from synthesis through place-and-route for large System-on-Chip (SOC) designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Role type
Senior Physical Design Engineer (IC)
Builds
Production silicon tape-outs of medium to large-size SOC blocks in advanced foundry process nodes
Domain
Semiconductor / Physical Design
Required skills
End-to-end Physical Design execution (synthesis, place-and-route, signoff), SOC clock construction and timing closure, Low-power design methodology, PPA trade-off analysis, Physical verification and EMIR, Formal equivalence checking, Data-driven flow optimization, Cross-functional collaboration
Preferred skills
Advanced foundry process node tape-out experience, High-speed clock construction strategies, RTL to GDS implementation expertise
Technologies
Synthesis tools, Place-and-route tools, Physical verification tools, EMIR tools, Formal equivalence tools, Low-power verification tools
Responsibilities
Drive end-to-end execution from synthesis through place-and-route for large designs, Ensure completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification, Drive methodology exploration activities to optimize SOC blocks for clock construction, Coordinate with CAD, RTL/Design teams, DFT, Architecture, Power & Performance, and Technology teams, Own complete PD execution of medium to large-size SOC blocks, Partner with PD flow/CAD and methodology teams to flag and fix PD TFM issues
Seniority
Senior, hands-on IC