Senior PCIe Design Engineer
Core
Design and integrate PCIe, CXL, and other IP for System-on-Chips (SoCs) within complex compute subsystems.
Role type
Senior IC digital design engineer (SoC/PCIe)
Builds
SoCs with integrated I/O subsystems (PCIe, CXL, UCIe, Ethernet)
Domain
Semiconductor / Hardware Design
Required skills
Digital hardware design, Verilog HDL, SoC development, PCIe/CXL/UCIe/Ethernet integration, Static design checks (CDC, RDC, X-Propagation, Linting), Scripting (Perl/Python)
Preferred skills
ARM-based designs, Team leadership, Synthesis and timing analysis, Power management, DFT, Physical implementation
Technologies
Verilog, Perl, Python, PCIe, CXL, UCIe, Ethernet, ARM IP
Responsibilities
Write micro-architecture specifications and develop RTL, Collaborate with verification and backend teams for debugging and timing closure, Evaluate and improve system performance, Guide and support team members, Balance project management activities
Seniority
Senior, hands-on IC
