ASIC Physical Design

1,648 open positions

SOC System Architect MediaTekHsinChu 7y Define and optimize SOC hardware architecture and associated software flows to improve system performance, power efficiency, and area.
Physical Design Engineer Squircle-It-Consulting-Services-Pvt-LtdBengaluru, KA, in $0k–$0k10y IC Physical Design Implementation for high-utilization, congestion, and timing-driven blocks.
SoC设计-d2d/c2c方向 ByteDance北京 Design SoC systems including specification definition, integration, IP selection, and RTL design, with a focus on die-to-die (d2d) and chip-to-chip (c2c) interfaces.
ASIC设计工程师（网络方向） ByteDance北京 Designing ASIC chips for data center networking applications, focusing on requirement analysis, micro-architecture design, and RTL development.
芯片综合/STA工程师（上海） ByteDance上海 Perform logic synthesis, formal verification, and STA signoff for SoC chips; collaborate on clock/reset schemes, low-power strategies, and timing closure.
芯片硬件架构设计工程师-视频编解码算法 ByteDance北京 Design high-efficiency, high-density, low-latency, and low-power video transcoding hardware solutions for data centers, including video encoding algorithms, C-models, and hardware architecture.
ASIC设计工程师（RDMA方向）-Data ByteDance北京 Design and develop ASIC chips for data centers, focusing on RDMA protocol implementation, micro-architecture, and RTL development.
芯片系统架构师-PICO ByteDance上海 Define MR product SOC architecture requirements, including external interfaces, custom IP, memory bandwidth, interconnect protocols, and power constraints.
NoC设计工程师-Data（深圳） ByteDance深圳 Design, develop, and integrate NoC systems for SoC chips, ensuring functional and performance targets are met with physical implementation alignment.
架构和性能分析工程师-Data（上海） ByteDance上海 Design SoC system architecture (SoC/CPU architecture and microarchitecture definition) and optimize server system performance and power consumption based on models.
SoC设计工程师-Data（北京） ByteDance北京 Define SoC specifications, perform SoC integration, IP selection, and RTL design for high-performance or advanced process SoCs.
SoC设计工程师（上海） - 芯片研发 ByteDance上海 Designing custom hardware optimization for ByteDance's business scenarios, including defining specs, SoC integration, IP selection, and RTL design for advanced semiconductor process cloud chips.
芯片架构师(北京/深圳) TencentShenzhen, China Designing and optimizing SoC architecture, including bus topology, QoS strategies, address translation, memory access behavior, and IO device-CPU cache consistency.
ASIC设计工程师（Scale up内存语义方向） - 芯片研发 ByteDance深圳 Designing ASIC chips for datacenter scenarios, focusing on scale-up memory semantics and high-speed interconnects to optimize performance and reduce costs for ByteDance's business.
SoC系统软件架构师/工程师-高速接口 ByteDance北京 Design and optimize system software architecture for ByteDance's self-developed SoC chips, focusing on high-speed interface debugging and silicon-to-product validation.
Senior SoC Digital Design Engineer, Multimedia Lab TikTokSan Jose, United States of America Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions (FPGA and ASIC).
芯片设计工程师 TencentShanghai, China Design, implement, and optimize digital chips, supporting verification and backend teams.
ASIC设计工程师-AI芯片 ByteDance北京 Design microarchitecture, RTL, and integration for ASIC chips in data centers, optimizing Power/Performance/Area (PPA) for AI accelerators.
芯片设计工程师(北京/上海/深圳) TencentShenzhen, China Design and implement SoC/IP systems and subsystems, focusing on module architecture, RTL implementation, timing analysis, and PPA optimization.
芯片设计工程师(北京/上海/深圳) TencentShanghai, China Design and implement SoC/IP systems and subsystems, focusing on module architecture, RTL implementation, timing analysis, and PPA optimization.
架构和性能分析工程师-Data（深圳） ByteDance深圳 Design SoC system architecture (SoC/CPU architecture and microarchitecture definition) and optimize server system performance and power consumption based on models.
ASIC设计工程师（网络方向） ByteDance上海 Design and develop ASIC chips for data center networking applications, focusing on microarchitecture and RTL implementation.
SOC ESL性能建模与分析工程师（上海） - 芯片研发 ByteDance上海 Develop ESL platforms for large-scale SoC chips, perform simulation and performance analysis based on ESL models, and explore and validate chip architectures.
SOC ESL性能建模与分析工程师（北京） - 芯片研发 ByteDance北京 Develop ESL platforms for large-scale SoC chips, perform simulation and performance analysis, and validate chip architecture solutions based on ESL performance models.
CPU ESL性能建模与分析工程师-Data（杭州） ByteDance杭州 Develop precise performance models for high-performance CPU cores, buses, and DDR; calibrate models against RTL; explore and simulate CPU/SoC architectures.
资深芯片软件系统分析师（稳定性和可管理性方向）-Data ByteDance北京 Design and deliver stability solutions for chip products in data center scenarios, optimizing software/hardware architectures to ensure reliability in critical business chains.
SoC Digital Design Engineer, Multimedia Lab TikTokSan Jose, United States of America Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions.
IC前端工程师/IP设计工程师-Data（深圳） ByteDance深圳 IC Front-end Engineer responsible for IP module detailed design, SOC integration, RTL design, and timing verification.
芯片综合集成Tech Leader - 芯片研发 ByteDance北京 Leading technical teams to deliver SoC chip logic synthesis, SDC/UPF, STA, formal verification, and low-power verification, ensuring full chip delivery for ByteDance's specialized business scenarios.
SoC系统软件架构师/工程师 - 芯片研发 ByteDance北京 Design and optimize system software architecture for self-developed SoC chips, supporting large-scale deployment in data centers and solving critical online issues.
芯片系统软件工程师-Data（杭州） ByteDance杭州 Define, develop, and deliver low-level software architectures for SoC chips, including bring-up, verification, and firmware development.
Director of Analog Design – Wearable SoCs (On-site. West Lafayette, USA) IxanaWest Lafayette, IN $175k–$175k Architect next-generation Wi-R SoCs integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces for brain-inspired wearable computing.
RTL Design & Integration Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Integrate internal and external IPs into top-level System-on-Chips (SoCs) for ultra-low-power, brain-inspired wearable compute systems.
Senior RTL Design Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Architect and design ultra-low-power digital systems and control/data path blocks for next-gen wearables using patented Wi-R technology.
ASIC设计工程师（Scale up内存语义方向） - 芯片研发 ByteDance上海 Design and develop ASIC microarchitecture and RTL for data center network chips, focusing on scale-up memory semantics and RDMA protocol optimization.
芯片系统架构师-PICO ByteDance北京 Define MR product SOC architecture requirements, internal data path control, and hardware/software partitioning to optimize performance, power, and area.
网卡芯片Tech Leader-Data ByteDance上海 Leading a team to define requirements, product specifications, architecture, and development plans for network interface card (NIC) chips.
网卡芯片Tech Leader-Data ByteDance北京 Leading a team to define requirements, product specifications, architecture, and development plans for network interface card (NIC) chips.
芯片性能架构师-服务器 ByteDance上海 Define and evolve server chip architectures aligned with data center application characteristics and system software features.
数字设计专家-PICO ByteDance上海 Lead digital design for custom image sensors in AR/VR products, defining block-level specs, RTL design, and integration.
ASIC设计工程师（DPU方向）-Data ByteDance上海 Design and develop RTL for Data Processing Unit (DPU) chips, supporting migration to ASIC and integration.
交换机硬件工程师-基础设施 ByteDance北京 Design, debug, and mass-produce data center switch CPU chips and subsystems (BMC, BIOS, SSD, DDR) while ensuring circuit design metrics, reliability, and consistency.
芯片性能架构师-服务器 ByteDance深圳 Design and optimize server chip architectures for data center applications, focusing on performance, power, and area (PPA) efficiency through software-defined architecture and workload analysis.
版图设计工程师（北京） - 芯片研发 ByteDance北京 Designing layout for specific hardware blocks to optimize performance and reduce costs for ByteDance's cloud and business-specific chips.
SoC设计工程师-Data（西安） ByteDance西安 Define SoC specifications, perform SoC integration, IP selection, and RTL design for System-on-Chip architectures.
ASIC设计工程师-AI芯片 ByteDance上海 Design microarchitecture, RTL, and integration for ASIC chips in data centers, optimizing Power/Performance/Area (PPA) for AI accelerators.
SoC架构工程师-AI芯片（上海） ByteDance上海 Designing the top-level architecture and subsystem integration for high-performance AI SoCs, ensuring efficient data interaction and reliability.
互联芯片架构师（技术规划） - 芯片研发 ByteDance深圳 Designing and planning interconnect chips for ByteDance's cloud infrastructure to optimize performance and reduce costs for specific business scenarios.

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