Senior Physical Design Engineer
Core
Lead end-to-end physical design execution from synthesis to signoff for flagship silicon projects, optimizing timing, power, and area (PPA) for large sub-chips and critical blocks.
Role type
Senior Physical Design Engineer (IC Design)
Builds
Production silicon chips and subsystems for flagship products
Domain
Semiconductor / VLSI Physical Design
Required skills
Floorplanning, Place-and-Route, Static Timing Analysis (STA), Clock Tree Synthesis (CTS), Physical Verification, EMIR, Formal Equivalence, Low-Power Verification, Design Planning (DP), Timing Constraints, DFT integration, ECO implementation, PPA optimization, Advanced scripting (Perl, TCL, Python), EDA tool integration
Preferred skills
Hierarchical design, Multi-voltage/multi-clock domain expertise, SOC design trade-offs, Mentorship
Technologies
Synopsys, Cadence, Perl, TCL, Python
Responsibilities
Lead floor-planning and design planning activities to optimize timing-critical and large sub-chips; Drive end-to-end execution from synthesis through place-and-route ensuring completion of all signoff stages; Make sound technical trade-offs between power, area, and timing; Partner with CAD and methodology teams to flag and fix PD TFM issues; Mentor engineers on technical aspects; Implement Engineering Change Orders (ECO) for power and timing convergence.
Seniority
Senior, hands-on IC
