SoC Design Director
Core
Lead the end-to-end design of high-performance digital controllers, bridges, and full-chip SoCs for rack-scale AI connectivity solutions.
Role type
SoC Design Director (Senior IC)
Builds
Custom connectivity chips integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies
Domain
Semiconductor / AI Infrastructure / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
RTL development, micro-architecture, timing closure, UVM-based verification, GDS implementation, processor IP integration, PCIe design, DMA engine design, pre/post-silicon debug, System Verilog/Verilog, Python/Perl scripting
Preferred skills
Secure boot implementation, RISC-V subsystem design, PAD design, DFT, floor planning, CI/CD design workflows, NIC/switch/storage product experience
Technologies
Synopsys, Cadence, UVM, System Verilog, Verilog, Python, Perl, ARM, ARC, RISC-V, PCIe, CXL, NVLink, UALink
Responsibilities
Design and implement high-performance digital solutions including RTL development and synthesis; Collaborate with cross-functional teams on IP integration for processor IPs and peripherals; Own block-level and full-chip designs from architecture to GDS at nodes ≤ 16nm; Ensure timing closure and oversee pre- and post-silicon debug; Utilize Synopsys/Cadence tools to ensure first-pass silicon success
Seniority
Director, hands-on IC leadership
