ASIC Design Engineer - Cache Controller
Core
Design and develop hardware for cache subsystems in high-performance System on a Chip (SoC) to optimize performance, area, and power consumption.
Role type
ASIC Design Engineer (Cache Controller)
Builds
Special-purpose cache and controller components for mobile SoC memory hierarchy
Domain
Semiconductor / Hardware Design
Required skills
RTL design, micro-architecture development, memory subsystem knowledge, PPA tradeoff analysis, netlist development, timing closure
Preferred skills
Cache design, multi-processor cache coherence protocols, high-performance coherent memory systems, high-performance DRAM controller
Technologies
RTL, SoC, memory subsystems, netlist, timing closure
Responsibilities
Develop cache micro-architecture based on guidelines and model analysis; Explore architecture trade-offs in system performance, area, and power; Develop and debug RTL design of cache subsystem sections; Work on front-end netlist and area/timing analysis; Collaborate with physical design team on timing closure.
Seniority
Entry-level (0 years industry experience)
