ASIC Verification Engineering
1,761 open positions
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Senior IP Verification Engineer NxpBangalore 4mo Pre-silicon verification of complex IP modules and subsystems including memory controllers and interconnects.
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Staff Digital Verification Engineer ON SemiconductorCork, Co. Cork, Ireland 4mo Verification of digital top-level subsystem IP for next-generation automotive and intelligent power applications within the TREO platform.
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Staff Verification Engineer ArmAustin, Texas $191k4mo Verifying functionality of High Speed IOs (PCIe, CXL) at the Sub-system level for next-generation SoCs.
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WiFi MAC Design Verification Engineer AppleSunnyvale, United States of America 4mo Verify the Wireless MAC block and sub-systems within Apple's System-on-Chip (SoC) designs to ensure high-quality Wi-Fi connectivity.
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Senior ASIC Design Verification Engineer - Terawave BlueoriginCentral Texas, US $230k4mo Lead verification planning and execution for complex digital subsystems in next-generation Satellite communication ASICs.
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Staff Engineer Verification InfineonBangalore BTP 4mo Architecting and executing verification strategies for complex ASIC subsystems and SoC integration, focusing on formal verification, fault injection, and AI-driven test case generation.
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Senior Verification Engineer NVIDIAIndia, Bengaluru 4mo Verify micro-architecture and architecture features for NVIDIA's next-generation CPUs and SoCs with AI capabilities, supporting applications in self-driving cars, gaming consoles, and automated machines.
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Senior Design Verification Engineer Texas InstrumentsBengaluru, Karnataka, India 5mo Lead chip-level design verification for advanced Ethernet PHY devices, focusing on DSP data path validation, FPGA emulation, and analog/mixed-signal system performance.
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MANAGER, DDEG DESIGN METHODOLOGY MicronHyderabad, Telangana, India 5mo Lead verification methodology and environments for advanced DRAM and emerging memory products, utilizing AI-driven automation to accelerate verification cycles.
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Lead Application Engineer CadenceRemote 5mo Lead Application Engineer for Emulation and Prototyping supporting customer engagements in deploying technical solutions and resolving issues.
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Senior AMS Verification Engineer Renesas-ElectronicsIstanbul, tr 5mo Lead verification planning and execution for analog IC components at block and full-chip levels, developing event-driven models and aligning verification goals with design intent.
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Senior Staff Engineer in Microcontroller Sub-System Verification- Cork, Ireland QualcommCork, Ireland 5mo Provide technical leadership for complex verification programs of microcontroller sub-systems, shaping methodology and execution strategy across IP and subsystem scopes to enable high-quality silicon delivery.
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Formal Verification - DV EtchedSan Jose 5mo Drive formal verification strategy and execution for custom IP, interface IP, and SoC subsystems in ASICs to prove design correctness and expose deep corner-case bugs.
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IC verification engineer MediaTekHsinChu 5mo Developing test patterns for chip bring-up and debugging post-silicon issues to identify design weaknesses.
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Staff Design Verification Engineer SiFiveHsinchu, Taiwan 5mo Ensuring fidelity of new highly configurable RISC-V CPU cores and related IPs for clients in autonomous driving, 5G, wearables, and IoT.
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SR Design Verification Engineer Advanced Micro Devices, IncSanta Clara, California 5mo Design Verification Engineer for high-performance ASICs in data center networking (DPU), developing UVM testbenches and debugging complex RTL/architecture issues.
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Digital Design Verification Engineer OlixBristol, UK 5mo Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, and deep pipelining in advanced CMOS nodes.
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Senior Quantum Design Verification Engineer MicrosoftUnited States, Washington, Redmond 5mo Define pre-silicon simulation and post-silicon validation plans for SoC and IP, creating verification environments and tests for RTL/netlist designs while managing repositories and bug tracking.
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Sr. Staff/Staff Design Verification Engineer CerebrasHeadquarters/Sunnyvale Office $250k5mo Develop and implement verification strategies, detailed tests, and coverage plans for the world's largest AI chip architecture to ensure high-quality design working on first silicon.
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Physical Design Verification Manager, Annapurna Labs
AmazonCupertino, California, United States
$201k5mo
Lead end-to-end physical verification strategy for AWS's most complex SoCs (≥100M gates) from floorplan to tape-out.
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Staff Verification Design Engineer SemtechIND - Hyderabad 5mo Perform block and chip-level verification across RTL, gate-level, and analog/mixed-signal domains to ensure tape-out quality and support post-silicon bring-up.
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