Staff Engineer Verification
Core
Architecting and executing verification strategies for complex ASIC subsystems and SoC integration, focusing on formal verification, fault injection, and AI-driven test case generation.
Role type
Staff Engineer, ASIC Verification
Builds
Production-ready verification environments and testbenches for power systems and IoT semiconductor solutions.
Domain
Semiconductor / ASIC Design / Hardware Verification
Required skills
SystemVerilog (SV), UVM, Formal Verification, Root Cause Analysis, Fault Injection, AI-driven test generation, RTL simulation, Gate-level simulation, Protocol knowledge (I2C, SPI, AHB/APB)
Preferred skills
ARM-based SoC verification, Power Aware simulation, Mentor Graphics (RNM), Matlab model integration
Technologies
SystemVerilog, UVM, DPI, RNM, Matlab, I2C, I3C, UART, AHB, APB, SMBUS, SPI
Responsibilities
Create Subsystem Verification plans for PMBUS and AVS interfaces; Execute Formal verification coverage for critical control interfaces; Develop SOC Integration verification and system level scenarios; Run Fault Injection Campaigns for ASIL-D Products; Perform GLS Verification and root cause analysis down to flop level; Demonstrate AI-driven productivity improvements in verification test case generation.
Seniority
Staff, hands-on IC with mentorship responsibilities
