Principal ASIC Design Verification Engineer - Terawave
Core
Technical authority defining end-to-end verification strategy for advanced ASICs enabling next-generation satellite communication systems.
Role type
Principal ASIC Design Verification Engineer
Builds
High-performance communication hardware for satellite constellations (LEO/MEO)
Domain
Aerospace / Satellite Communications / ASIC Design
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, verification signoff methodology, formal analysis, emulation, silicon correlation, root-cause analysis, VIP development, regression automation, technical leadership
Preferred skills
Space-based communications, digital modems, phased-array processing, fault tolerance, radiation-aware verification, hardware/software partitioned systems
Technologies
System Verilog, UVM, formal verification tools, emulation platforms
Responsibilities
Define end-to-end verification strategy for large Satellite communication ASIC or SoC programs; Establish verification methodologies, infrastructure, and signoff criteria across block, subsystem, and SoC levels; Lead verification planning for complex communication functions such as modem pipelines, FEC engines, digital beamforming, packet processing, and control fabrics; Evaluate verification completeness through coverage, assertions, formal analysis, emulation, and silicon correlation; Resolve critical technical issues and direct root-cause analysis for the most complex functional failures; Guide development of reusable VIP, reference models, and regression automation frameworks; Mentor technical leaders and raise the overall verification maturity of the organization; Influence future verification roadmap, tool strategy, and reuse models.
Seniority
Principal, technical authority & mentorship
