Principal IP verification engineer
Core
Verify complex IPs including memory controllers and interconnects to ensure functional correctness and quality metrics.
Role type
Principal IP verification engineer
Builds
Scalable SystemVerilog/UVM-based verification environments with reusable components for memory controllers and interconnects
Domain
Semiconductor IP verification, memory controllers, interconnect protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Verilog, Functional verification methodologies, Assertions (SVA), coverage analysis, interconnect protocols (AXI, AHB, CHI, PCIE), RTL debugging, regression management
Preferred skills
Formal verification
Responsibilities
Develop and execute verification plans for memory controllers and interconnects; Build scalable verification environments; Own end-to-end IP verification sign-off; Achieve high-quality metrics including functional and code coverage; Manage regressions and debug failures; Collaborate with design teams to resolve issues
