Principal Verification Engineer
Core
Lead end-to-end verification execution for complex Digital IP and Subsystem designs to ensure high quality and first-pass silicon success.
Role type
Principal IC Digital IP Verification Engineer
Builds
Complex Digital IP and Subsystem verification programs
Domain
Semiconductor / Digital SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, C/C++, Verilog, VHDL, VCS, NCSim, ModelSim, Questa, testbench architecture, functional coverage, assertions (SVA), regression management, ARM cores, AHB, AXI, AMBA, memory subsystems (SRAM, Flash, DDR, memory controllers)
Preferred skills
formal verification, gate-level simulation, emulation, automotive domain, graphics/vision accelerators, high-speed serial interfaces, Ethernet
Technologies
SystemVerilog, UVM, C, C++, Verilog, VHDL, VCS, NCSim, ModelSim, Questa, ARM, AHB, AXI, AMBA
Responsibilities
Lead end-to-end verification execution for complex IPs and Subsystems; Evaluate, adopt, and deploy advanced and scalable verification methodologies; Own verification quality metrics across planning, execution, and closure phases; Drive 'Zero Defect' mindset through rigorous process adherence, coverage closure, and defect prevention strategies; Analyze existing verification flows and implement improvements to enhance efficiency, predictability, and quality; Contribute to and influence technical innovation within the team, including methodology evolution and automation; Support pre-silicon and post-silicon validation activities where required
Seniority
Principal, hands-on IC
