Staff Engineer, ASIC Design Verification
Core
Developing advanced verification components for complex System-on-Chip (SoC) designs, including simulation environments and test plans.
Role type
Staff Engineer, ASIC Design Verification
Builds
Verification components for NAND, DDR, and PCIe IP/sub-systems within complex SoC designs.
Domain
Semiconductor / Memory and Storage / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, constrained random verification, functional coverage closure, SoC test plan definition, NAND/DDR/PCIe IP knowledge, ASIC simulation tools, debugging complex problems
Technologies
UVM, System Verilog, ASIC simulation tools
Responsibilities
Develop new simulation environments, execute verification plans, interface with design teams, debug complex problems, define block/sub-system/SoC top-level test plans
Seniority
Senior, hands-on IC
