Digital Design Verification Engineer
Core
Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, and deep pipelining in advanced CMOS nodes.
Role type
Senior Digital Design Verification Engineer
Builds
High-speed, real-time data-processing silicon (ASICs/SoCs) for AI hardware
Domain
Semiconductor hardware design and verification (CMOS, high-speed interfaces)
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random testing, coverage closure, formal verification, assertion-based verification, CDC/RDC analysis, MATLAB/Simulink, Python, high-speed IP verification (SerDes, DDR/HBM, PCIe, Ethernet)
Preferred skills
Tape-out experience on advanced process nodes, formal verification tools (Jasper), coherent optical links, photonic-electronic co-design, AI/ML workloads, systolic arrays, arithmetic pipeline verification, processor/ISA verification
Technologies
SystemVerilog, UVM, CocoTB, Jasper, MATLAB, Simulink, Python, NumPy
Responsibilities
Develop and maintain comprehensive verification environments; define and implement assertion-based verification strategies; apply formal verification techniques; model and validate algorithms; support FPGA prototyping and silicon bring-up; collaborate with digital, optical, mixed-signal, and software teams; analyze verification results and drive design fixes; contribute to verification methodology development and mentor junior engineers
Seniority
Senior, hands-on IC