Design Verification Engineer
Core
Verify innovative, high-throughput cellular baseband modems and transceiver link controllers for Apple's SOCs.
Role type
Senior IC design verification engineer (cellular systems)
Builds
Next-generation cellular systems (baseband modems, RF link controllers) for Apple devices
Domain
Consumer electronics / Cellular communications / ASIC design
Deliverable
production ML models
Required skills
UVM, System Verilog, System C, C/C++, Python, constraint random testing, SVA, coverage-driven verification, test planning, LLMs for verification, Python automation
Preferred skills
4G/5G physical layer (3GPP), embedded processor core verification, Bus Fabric/NOC/AXI/AHB verification, prompt engineering, C/C++ modeling
Technologies
UVM, System Verilog, System C, Python, LLMs, 3GPP
Responsibilities
Construct detailed test plans for design components; Create coverage-driven verification plans; Architect reusable UVM test benches; Implement ML-driven workflows to enhance verification; Debug failures from RTL simulation to sign-off; Maintain regressions and report coverage metrics.
