Senior Quantum Design Verification Engineer
Core
Define pre-silicon simulation and post-silicon validation plans for SoC and IP, creating verification environments and tests for RTL/netlist designs while managing repositories and bug tracking.
Role type
Senior IC design verification engineer (SoC/IP)
Builds
High-quality SoC and IP designs ready for silicon
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verification principles, testbench creation, stimulus generation, simulation environment development, debugging complex designs, chip/computer architecture knowledge, analog/digital interface verification, scripting (Python/Ruby/Perl), C/C++ programming, analog mixed-signal modeling, silicon characterization, automation of simulation/data analysis
Preferred skills
AI-assisted verification flows, performance modeling, research gathering, task automation using modern AI tools
Technologies
Python, Ruby, Perl, C, C++, MATLAB, Visual Studio Code
Responsibilities
Create testplans for pre-silicon simulation including digital and analog components; collaborate with DFT teams to test DFT features; align verification methodologies with wider teams; drive continuous improvement to verification processes; manage databases and flows for SoC/IP repositories; setup and manage bug-tracking systems; drive milestone reviews and status reports; validate designs in simulation with pre and post layout RTL/netlists; perform analog mixed-signal simulation models; collaborate with architects, analog mixed-signal designers, physical design, and DFT teams
Seniority
Senior, hands-on IC
