Staff Verification Design Engineer
Core
Perform block and chip-level verification across RTL, gate-level, and analog/mixed-signal domains to ensure tape-out quality and support post-silicon bring-up.
Role type
Staff IC verification engineer (digital/AMS)
Builds
ASIC chips and integrated circuits
Domain
Semiconductor hardware design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, RTL/gate-level debugging, formal verification, Python/Perl scripting, ASIC design flow knowledge, regression test management, coverage analysis
Preferred skills
UVM environment setup from scratch, VHDL, RNM, analog behavioral modeling, verification flow automation
Technologies
System Verilog, UVM, Python, Perl, VHDL, RNM, formal verification tools
Responsibilities
Create verification strategy and detailed plans; develop tests and run regressions; support post-silicon bring-up and ATE testing; improve verification scalability via environment enhancement and tool automation; participate in design reviews with verification perspective
Seniority
Staff, hands-on IC with strategic oversight
