Staff Verification Design Engineer
Core
Perform block and chip-level verification in register-transfer level (RTL), gate-level, and analog/mixed-signal (AMS) to ensure tape-out quality.
Role type
Staff IC verification engineer (digital/AMS)
Builds
ASIC chips and integrated circuits
Domain
Semiconductor / Hardware Design
Required skills
System Verilog, UVM, RTL verification, gate-level verification, analog/mixed-signal verification, formal verification, regression testing, coverage analysis, Python scripting, Perl scripting, ASIC design flow knowledge, debugging digital simulations
Preferred skills
UVM environment setup from scratch, VHDL, RNM, verification flow automation, analog behavioral model development
Technologies
System Verilog, UVM, Python, Perl, RTL, Gate-level, AMS, Formal Verification, ATE
Responsibilities
Perform block and chip-level verification in RTL, gate-level, and AMS; Run digital/mixed-signal simulations and formal verification; Create verification strategy and detailed verification plans; Develop tests, run regressions, and monitor coverage; Support post-silicon bring-up and debug for bench validation and ATE testing; Improve verification scalability and portability through environment enhancement and tools automation
Seniority
Staff, hands-on IC
