Principal Engineer - Memory Circuit Design Verification
Core
Lead verification architecture and methodology for next-generation DDR memory designs, leveraging AI/ML tools to optimize verification efficiency and debug turnaround.
Role type
Principal Engineer - Memory Circuit Design Verification
Builds
Next-generation DDR memory chips and verification infrastructure
Domain
Semiconductor / Memory / Design Verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, verification architecture, coverage strategies, AMS Co-Simulation, Python/TCL/Perl scripting, AI/ML for verification optimization, EDA tool integration
Preferred skills
DDR/GDDR memory verification experience, mixed-signal verification flows, AI-assisted regression analysis, predictive coverage gap analysis
Technologies
UVM, SystemVerilog, Python, TCL, Perl, EDA tools, AI/ML platforms
Responsibilities
Define verification architecture and methodology, develop verification plans and sign-off criteria, architect UVM-based testbenches, mentor verification engineers, integrate AMS Co-Simulation, collaborate with build teams, leverage AI/ML for failure classification and debug analytics
Seniority
Principal, hands-on IC with mentorship
