Senior Verification Engineer
Core
Verify RTL implementing new features in Arm-based SoCs to ensure functionality meets architectural and quality requirements.
Role type
Senior IC verification engineer (SoC/RTL)
Builds
Arm-based System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, Verilog, UVM, constrained-random verification, verification strategy development, SoC verification flows, Python/Perl scripting, debugging complex design issues
Preferred skills
Arm system architectures, AMBA protocols (CHI, AXI, AHB, APB), JTAG/SWD/TAP debug, clock domain crossing (CDC), reset domain crossing (RDC), power-aware verification (UPF/CPF), DFT concepts (scan, MBIST)
Technologies
SystemVerilog, Verilog, UVM, Python, Perl, AMBA, JTAG, SWD, TAP, UPF, CPF
Responsibilities
Collaborate with RTL designers and architects to understand specifications; Develop and improve validation setups, stimulus generation, and coverage infrastructure; Create and execute verification and test plans; Drive functional and code coverage closure; Debug and resolve sophisticated design issues; Mentor less experienced engineers
Seniority
Senior, hands-on IC
