Principal DFT Engineer
Core
Design and verify Digital Front-End (DFT) architectures for next-gen automotive processing, edge processing, and radar products.
Role type
Principal DFT Engineer (IC)
Builds
Scan architectures, JTAG, memory BIST, and ATPG patterns for automotive MCUs/MPUs
Domain
Automotive semiconductor design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL coding (Verilog/VHDL), Scan insertion, JTAG, Memory BIST, ATPG, DRC analysis, ATPG coverage analysis, Power-aware simulation, Wafer probe bringup, Regression suite management
Preferred skills
Debugging simulation failures, Timing/SDF analysis, NXP DFT flows
Technologies
Verilog, VHDL, NXP DFT flows, ATPG, SDF
Responsibilities
Handle RTL design for DFT changes at subsystem and top levels; Insert and verify MBIST RTL; Analyze and fix Scan DRCs; Analyze ATPG reports and generate patterns for ATE; Insert TAP, IOs, and Test Pinmux; Manage power-aware RTL/GLS simulation and regression suites; Bring up patterns on wafer probe and final test.
Seniority
Senior, hands-on IC
