Principal Engineer - Memory Circuit Design Verification
Core
Architecting and implementing verification strategies for next-generation DDR memory designs using AI/ML tools to optimize efficiency and debug turnaround.
Role type
Principal IC memory circuit design verification engineer
Builds
Production verification environments and sign-off criteria for high-performance DRAM and storage products
Domain
Semiconductor memory (DDR/GDDR) and EDA
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, verification architecture, coverage strategy, AMS Co-Simulation, Python/TCL/Perl scripting, AI/ML concepts (supervised learning, clustering, anomaly detection), regression management
Preferred skills
Mixed-signal verification flows, AI-assisted EDA tools, AI-driven waveform/debug analytics
Technologies
UVM, SystemVerilog, Python, TCL, Perl, EDA tools
Responsibilities
Define verification architecture and methodology for next-gen DDR designs; Develop verification plans, coverage strategies, and sign-off criteria; Architect and implement UVM-based testbenches and reusable components; Mentor verification engineers on guidelines and advanced methodologies; Evaluate and integrate AMS Co-Simulation techniques; Leverage AI/ML tools to improve verification efficiency and debug turnaround time; Contribute to automation initiatives like intelligent test generation and predictive coverage gap analysis
Seniority
Principal, hands-on IC with mentorship
