SR Design Verification Engineer
Core
Design Verification Engineer for high-performance ASICs in data center networking (DPU), developing UVM testbenches and debugging complex RTL/architecture issues.
Role type
Senior IC Design Verification Engineer
Builds
High-performance DPU and software stack for data centers and cloud environments
Domain
Semiconductor / Data Center Networking / ASIC Design
Required skills
SystemVerilog, UVM, Debugging (RTL/Architecture), Constrained-random verification, Simulation tools (VCS, Verdi), Protocol knowledge (PCIe, AXI, Ethernet, DDR), Scripting (Python/Tcl)
Preferred skills
Performance verification, Power-aware verification (UPF), Formal verification, FPGA/HAPS validation, C/C++ modeling
Technologies
VCS, Verdi/DVE, Python, Tcl, Make, UVM, SystemVerilog
Responsibilities
Develop UVM-based testbench architectures for IP, subsystem, and SoC levels; Drive test plan creation and coverage strategy; Execute verification plans and perform regression triage; Debug architectural, functional, and performance issues across RTL and interfaces; Optimize simulations and coverage closure; Mentor junior engineers and provide technical leadership.
Seniority
Senior, hands-on IC
