MANAGER, DDEG DESIGN METHODOLOGY
Core
Lead verification methodology and environments for advanced DRAM and emerging memory products, utilizing AI-driven automation to accelerate verification cycles.
Role type
Senior IC verification manager (DRAM)
Builds
Verification environments, test benches, and test vectors for DDR4/LPDDR4/DDR5/LPDDR5 chips
Domain
Semiconductor memory (DRAM) design verification
Deliverable
production ML models
Required skills
Verification methodology, full chip gate level simulation, debugging, test bench development, regression analysis, AI/ML-assisted design flows, automation frameworks, cross-site collaboration
Preferred skills
DRAM domain knowledge (DDR5, LPDDR5), agentic AI workflows, advanced automation in verification
Technologies
Agentic AI, simulation tools, regression analysis tools
Responsibilities
Guide verification effort direction, lead cross-site methodology development, provide technical advice to senior management, establish best known methods (BKM), simulate and debug pre-silicon designs, drive development of test benches using AI tools, integrate AI-driven flows with CAD/EDA teams
Seniority
Senior, hands-on IC
