Sr. Staff/Staff Design Verification Engineer
Core
Develop and implement verification strategies, detailed tests, and coverage plans for the world's largest AI chip architecture to ensure high-quality design working on first silicon.
Role type
Sr. Staff Design Verification Engineer (AI chip architecture)
Builds
Cerebras Wafer-Scale Engine (WSE) AI chip
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, DPI, Python, Perl, simulation, emulation, silicon bring-up, coverage collection, gate-level simulation, object-oriented design
Preferred skills
pipelined processor architecture knowledge
Technologies
simulators, waveform viewers, build and run automation, coverage collection tools, gate level simulators
Responsibilities
Develop and implement verification strategies and coverage plans based on micro-architecture; Create verification methodologies and reusable environments including stimulus, checkers, and assertions; Implement tests, manage regressions, and debug test failures; Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases; Continuously enhance verification infrastructure and flows; Contribute to the evolution of overall verification methodology and best practices.
Seniority
Sr. Staff, hands-on IC