Digital Design Verification Engineer | Precision ADC
Core
Develop SystemVerilog/UVM testbenches to verify digital logic, calibration algorithms, and mixed-signal interfaces of high-resolution delta-sigma ADC signal chains.
Role type
Digital Design Verification Engineer (Delta-Sigma ADC)
Builds
High-precision data converters for medical, industrial, automotive, and instrumentation applications
Domain
Analog/Mixed-Signal Semiconductor Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random stimulus, functional coverage models, assertions, regression campaign execution, RTL design fundamentals, mixed-signal interface verification
Preferred skills
EDA simulation tools (VCS, Xcelium, Questa), waveform debug, Python/Perl scripting, ADC architecture knowledge, noise and sampling concepts
Technologies
SystemVerilog, UVM, VCS, Xcelium, Questa, Python, Perl
Responsibilities
Develop constrained-random stimulus environments, write functional coverage models and assertions, run regression campaigns, triage simulation failures, participate in design and verification reviews
Seniority
Mid-level, hands-on IC