ASIC Verification Engineering
1,763 open positions
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ASIC DFT CAD Technical Leader CiscoSan Jose, California, US $184k6mo Lead end-to-end DFT flow architecture and build scalable CAD infrastructure for complex ASIC designs.
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Design Validation Product Engineer, DEG Technology MicronBoise, ID - Main Site 6mo Validating new DRAM products by focusing on real-silicon behavior through bring-up, characterization, and debug.
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Senior Performance Verification Engineer NVIDIAUS, CA, Santa Clara $136k–$265k6mo Define, plan, and execute performance verification strategy for sophisticated CPU designs, analyzing workloads and benchmarks to identify bottlenecks.
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SoC Physical Design Verification Engineer (M, F, D) AppleMunich, Germany 6mo Physical verification of high-performance, power-efficient system-on-chip (SoC) processors to ensure seamless device performance.
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Sr. Physical Design Verification Engineer, Annapurna Labs
AmazonCupertino, California, United States
$159k6mo
Ensure quality and manufacturability of complex semiconductor designs through physical verification processes for custom chips and accelerators.
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Senior Staff Engineer Verification InfineonBangalore BTP (India) 6mo Verification of complex SoCs/IPs, creating test plans/bench architecture, and driving verification closure using SV/UVM.
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Senior FPGA/Emulation Validation Engineer AxiadoSan Jose, CA, us $80k6mo Design verification, debugging, and system integration for SOC architecture using FPGA and emulation platforms to achieve pre-silicon goals.
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SOC设计工程师(In-System Test方向) MBJ20260430 MediaTekBeijing 6mo Designing and verifying In-System Test (IST) architectures, IP, and subsystems for SoC development.
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Design Verification Engineer ArmBengaluru, India 6mo Verify new ARM architectural features using in-house random instruction simulators and RTL prototypes to ensure functionality and performance compliance.
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Lead Design Engineer - Verification CadenceSHANGHAI 6mo Lead VLSI Design Verification Engineer developing and executing verification plans for SOC and IP blocks to ensure design intent and testability.
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UVM Verification specialist for ASIC and/or FPGA development AfryPune, MH, in 6mo UVM Verification specialist for complex ASIC and FPGA designs in the telecom sector, ensuring functional correctness and performance through advanced verification methodologies.
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Design Verification Engineer - APS Texas InstrumentsSanta Clara, CA, United States 6mo Confirm accuracy of analog and mixed signal electronic designs before mask development through independent analysis, experimental testing, and software simulations.
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Principal Engineer, Design Verification Engineering AnalogdevicesIreland, Dublin 6mo Lead design verification for mixed-signal power converter controllers from architecture through silicon bring-up, ensuring tape-out readiness and quality metrics.
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Design Verification Engineer - SoC EtchedAustin 6mo Verify performance features of custom IPs (systolic arrays, DMA engines, NoCs) and correlate with performance models across the hardware-software stack.
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