Staff Design Verification Engineer, HBM Architecture
Core
Design and scale verification solutions for next-generation High Bandwidth Memory (HBM) DRAM products used in AI and ML applications, focusing on 2.5D & 3D package integration and low power per bit.
Role type
Staff Design Verification Architect (HBM)
Builds
Custom digital and RTL2GDS flow verification solutions for HBM stacks
Domain
Semiconductor / Memory / AI Hardware
Deliverable
production ML models | product features
Required skills
Digital verification (Verilog), Analog verification (FastSpice), Mixed-signal verification, Custom design verification, RTL design verification, Testbench architecture, SoC verification methodologies, 2.5D & 3D package integration, Root cause analysis, Feasibility analysis
Preferred skills
Memory product verification (JEDEC/HBM), Verification flow development from scratch, Patent or publication history in verification
Technologies
Verilog, FastSpice, TSV, RTL2GDS
Responsibilities
Develop turnkey verification solutions based on customer look-ahead information; Drive co-verification through direct customer interactions; Build verification methodology improvements and GenAI applications; Debug pre-silicon and post-silicon issues and explore new architectures
Seniority
Staff, hands-on IC with mentorship