Formal Verification - DV
Core
Drive formal verification strategy and execution for custom IP, interface IP, and SoC subsystems in ASICs to prove design correctness and expose deep corner-case bugs.
Role type
Senior IC Formal Verification Engineer (ASIC DV)
Builds
ASIC chips for frontier intelligence inference workloads (compute arrays, DMA, NoCs, memory, PCIe, Ethernet, CPU subsystems)
Domain
Semiconductor hardware design / ASIC verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, SystemVerilog Assertions, formal verification methodology, commercial formal tools (Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal), digital design/architecture, RTL debugging, assumption/constraint modeling, coverage analysis
Preferred skills
Systolic array verification, protocol compliance checking, black-box IP verification, Python/TCL/Perl scripting, sequential LEC, floating-point proofs
Responsibilities
Define formal verification strategy for complex IP and SoC integration; Develop formal verification plans for functional correctness and deadlock/livelock freedom; Build reusable formal environments with abstractions and checkers; Drive proof convergence using assume-guarantee reasoning and coverage metrics; Translate design intent into high-value formal properties; Debug complex RTL and integration bugs using counterexamples; Contribute to formal sign-off methodology and regression automation
Seniority
Senior, hands-on IC
