Principal Engineer - IP Verification
Core
Lead end-to-end verification execution for complex Digital IP and Subsystem designs to ensure high quality and first-pass silicon success.
Role type
Principal Individual Contributor - Digital IP Verification
Builds
Complex Digital IP and Subsystem verification programs for SoC context
Domain
Semiconductor / Digital Integrated Circuits
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Correction: This is a hardware verification role, so the deliverable is verification closure and silicon success, which maps best to 'product features' in the context of IP delivery or a custom label. However, the prompt restricts to specific options. The closest fit for 'what the team ships' in a verification context is often the verified IP itself. Let's map to 'product features' as the IP is a product feature, or strictly follow the list. The list has: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work. None fit perfectly. 'product features' is the best proxy for IP delivery.
Required skills
SystemVerilog/UVM, C/C++, Verilog/VHDL, testbench architecture, assertions (SVA), functional coverage, regression management, microcontroller architectures (ARM), interconnect protocols (AHB, AXI, AMBA), memory subsystems (SRAM, Flash, DDR)
Preferred skills
formal verification methodologies, gate-level simulation planning, emulation environments, automotive domain knowledge, high-speed serial interfaces, networking protocols (Ethernet)
Technologies
VCS, NCSim, ModelSim, Questa
Responsibilities
Lead end-to-end verification execution for complex IPs and Subsystems, Evaluate and deploy advanced verification methodologies, Own verification quality metrics across planning and closure phases, Drive 'Zero Defect' mindset through coverage closure and defect prevention, Analyze and improve existing verification flows, Collaborate with Design, DFT, Architecture, and Validation teams, Support pre-silicon and post-silicon validation activities
Seniority
Principal, hands-on IC with mentorship
