Design Verification Engineer
Core
Verify innovative, high-throughput cellular baseband modems and transceiver link controllers for Apple's SOCs to ensure quality and reliability of next-generation cellular systems.
Role type
Senior IC design verification engineer (cellular baseband)
Builds
Next-generation cellular systems (baseband modems, RF link controllers) for Apple SOCs
Domain
Semiconductor / Cellular Communications (4G/5G)
Deliverable
production ML models
Required skills
UVM, System Verilog, System C, C/C++, Python, constraint random testing, SVA, coverage-driven verification, test planning, LLMs for verification, Python-based automation
Preferred skills
C/C++ modeling, 3GPP physical layer knowledge, embedded processor core verification, Bus Fabric/NOC/AXI/AHB verification, prompt engineering, LLM workflow optimization
Technologies
UVM, System Verilog, System C, Python, LLMs, 3GPP
Responsibilities
Construct detailed test plans for design components; Create coverage-driven verification plans; Architect UVM-based reusable test benches; Leverage LLMs to enhance verification processes; Design and implement ML-driven workflows; Implement test plans from RTL simulation to sign-off; Maintain regressions and report verification progress.
Seniority
Senior, hands-on IC
