Senior ASIC Design Verification Engineer - Terawave
Core
Lead verification planning and execution for complex digital subsystems in next-generation Satellite communication ASICs.
Role type
Senior ASIC Design Verification Engineer
Builds
High-quality silicon for TeraWave satellite communications network
Domain
Space-based communications / Satellite networks
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, verification planning, assertions, coverage closure, RTL debugging, digital control and datapath logic verification
Preferred skills
Space/wireless communications background, LDPC/BCH/FEC verification, formal verification, low-power verification, CDC/RDC verification, high-speed interface verification
Technologies
System Verilog, UVM, formal verification tools
Responsibilities
Lead verification planning and execution for complex blocks; Develop UVM environments, reference models, scoreboards, and assertions; Drive functional coverage closure and regression health; Identify verification gaps and corner cases; Collaborate with design, DFT, firmware, and physical design teams; Mentor junior engineers; Support bring-up, emulation, and post-silicon debug
Seniority
Senior, hands-on IC
