Staff Digital Verification Engineer
Core
Verification of digital top-level subsystem IP for next-generation automotive and intelligent power applications within the TREO platform.
Role type
Staff Digital Verification Engineer
Builds
Robust functionality and performance for automotive and intelligent power subsystems
Domain
Automotive semiconductor / Digital verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained random verification, formal verification, testbench architecture, scoreboards, monitors, checkers, functional/code coverage, Questa simulation tools
Preferred skills
automotive/high-reliability semiconductor experience, mixed-signal verification, AI-enabled verification flows (coverage acceleration, intelligent stimulus generation, debug automation), large SoC-level design flows, scripting (Python, Tcl)
Technologies
SystemVerilog, UVM, Questa (Mentor/Siemens), Python, Tcl
Responsibilities
Develop and execute constrained random verification environments; Architect and implement testbenches (scoreboards, monitors, stimulus generators, checkers); Define and track functional and code coverage; Perform and integrate formal verification techniques; Debug complex system-level issues across digital and mixed-signal boundaries; Collaborate with digital design, analog/mixed-signal design, and system architecture teams; Contribute to verification strategy and methodology improvements
Seniority
Staff, hands-on IC with strategy contribution
