Senior Design Verification Engineer
Core
Lead chip-level design verification for advanced Ethernet PHY devices, focusing on DSP data path validation, FPGA emulation, and analog/mixed-signal system performance.
Role type
Senior IC design verification engineer (analog/mixed-signal)
Builds
High-speed Ethernet PHY chips for industrial and automotive applications
Domain
Semiconductors / High-speed data / Analog & Mixed-Signal
Deliverable
production ML models | product features
Required skills
Verilog, Matlab, Python, FPGA-based emulation, analog/mixed-signal modeling, DSP fundamentals (filters, signal processing, sampling, modulation), RTL design review, test-bench development, debug leadership
Preferred skills
System-level DV, synthesizable channel model architecture, pre-silicon verification, digital power estimation
Technologies
Verilog, Matlab, Python, FPGA
Responsibilities
Study specifications and review RTL to create test cases for coverage; Develop test-benches for module, DUT, and system-level verification; Lead debug efforts for critical features; Work on FPGA-based emulation and prototyping; Lead synthesizable modeling for analog and channel models; Analyze simulation/emulation results to improve design quality; Document models, assumptions, and results.
Seniority
Senior, hands-on IC