Design Verification Engineer
Core
Design Verification Engineer ensuring quality and reliability of next-generation cellular systems (baseband modems and RF link controllers) for Apple's SOCs.
Role type
Senior IC Design Verification Engineer
Builds
Reusable UVM verification environments, comprehensive test cases, and ML-driven verification workflows for cellular IP and subsystems.
Domain
Semiconductor / Cellular Communications (4G/5G)
Deliverable
production ML models
Required skills
UVM, System Verilog, System C, C/C++, Python, Perl, Constraint Random Testing, SVA, Coverage Driven Verification, Test Planning, LLMs, MCPs, Python-based automation
Preferred skills
C/C++ modeling, 3GPP physical layer knowledge, Embedded processor core verification, Bus Fabric/NOC/AXI/AHB verification, Prompt engineering
Technologies
UVM, System Verilog, System C, Python, LLMs, MCPs, 3GPP
Responsibilities
Construct detailed test plans for design components; Create coverage driven verification plans; Architect UVM-based reusable test benches; Leverage LLMs to enhance verification processes; Design and implement ML-driven workflows; Implement test plans from RTL simulation to sign-off; Maintain regressions and report verification progress.
Seniority
Senior, hands-on IC
