Senior IP Verification Engineer
Core
Pre-silicon verification of complex IP modules and subsystems including memory controllers and interconnects.
Role type
Senior IC IP verification engineer
Builds
Verified IP modules and subsystems for integration into SoCs
Domain
Semiconductor hardware design, memory systems, interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, System Verilog, C/C++, RTL simulation, regression testing, functional coverage, directed and constrained random methodologies, formal verification, memory controller verification, interconnect protocols (AHB/AMBA), cache coherency, microcontroller/microprocessor architecture
Preferred skills
Perl, TCL, Python scripting, gate-level and FPGA debugging, emulation platform experience
Responsibilities
Define and write IP verification plans based on requirements; architect and develop UVM-based verification environments for RTL simulation; create test cases, stimulus, and assertions; execute verification plans and run regressions; debug designs pre- and post-silicon across simulation and emulation platforms; analyze code and functional coverage.
Seniority
Senior, hands-on IC
