ASIC Verification Engineering
931 open positions
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Principal Design Verification Engineer NxpPune 2mo Design verification for wireless communication ASICs, focusing on digital IP blocks, circuit calibration, DSP, and CPU subsystems.
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Application Engineer Manager Siemens-EdaSanta Clara, CA, United States $167k–$167k3mo Lead a Field Application Engineering team to drive technical sales and customer engagements for Hardware Assisted Verification (HAV) portfolio, leveraging expertise in hardware emulation, FPGA prototyping, and power verification.
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Senior Verification Engineer FractileThe Crescent 3mo Pre-silicon RTL verification for high-performance ML/AI ICs targeting data center scale-out applications.
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ASIC Design Verification Engineer, Technical Leader CiscoSan Jose, California, US $184k–$184k3mo Lead ASIC design verification for Silicon One hardware platforms, ensuring verification closure through simulation, emulation, and bring-up for Cisco's core Switching, Routing, and Wireless products.
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Director - IP Engineering (Technical Program Management ) GlobalFoundriesHsinchu 3mo Lead the development of high-performance compute processor IP products and drive execution strategy for multi-site R&D teams.
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DFT Engineer BroadcomUSA-TX-Austin - River Place B7 $129k–$129k3mo Design and implement Digital Design Test (DFT) solutions including MBIST, scan insertion, and ATPG to ensure silicon yield and debugability.
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Staff Engineer - DV SifiveBengaluru, Karnataka, India 3mo Hands-on development of high-performance CPU verification using System Verilog and UVM methodology.
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Staff Silicon Power & Performance Engineer (System Level Test & Characterization) ArmBengaluru, India 3mo Plan and execute silicon power, performance, and thermal characterization activities across multiple projects to ensure flawless silicon performance.
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ASIC Verification - Team Lead MicrosoftUnited States, California, Santa Clara 3mo Leads pre-silicon verification strategies, test plans, and environments for complex SoC, subsystem, and IP flows to ensure design quality and performance.
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Verification Lead (Lead DV) LumilensSan Jose 3mo End-to-end verification lead for a first-of-its-kind chiplet, defining methodology, coverage strategy, and regression infrastructure before RTL availability.
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?Software Engineer Test & Verification (d/w/m) Lindenberg im Allgäu, BAYERN 3mo Define requirements for PLD/FPGA testing and equipment, develop and execute verification tool qualifications, and analyze customer products.
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Senior Verification Engineer, SoC NVIDIAUS, CA, Santa Clara $136k–$136k3mo Define verification strategies and build verification infrastructure for next-generation AI-enabled System-on-Chip (SoC) ASICs.
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Senior Staff Engineer, GPU Design Verification (Formal Verification) Samsung Electronics3655 N 1st St, San Jose, CA, USA $198k–$198k3mo Shape block and subsystem level formal verification strategy and execution for Samsung's next-generation mobile GPU, ensuring functional correctness, power gating mechanisms, and architectural intent.
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Formal Verification Engineer AccentureBengaluru 3mo Ensure design correctness using mathematical methods like model checking and equivalence checking to detect corner-case bugs early in the design cycle.
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ASIC Verification Engineer HpeBengaluru, Karnātaka, India 3mo Architect and build block-level, subsystem, and full-chip verification environments for complex ASICs using SystemVerilog and UVM, ensuring tape-out readiness through rigorous functional and code coverage analysis.
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Principal Design Engineer CadenceBANGALORE 3mo Lead digital verification strategy and architecture for semiconductor/ASIC/SoC projects, defining methodologies, environments, and sign-off criteria.
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Manager, ASIC DV MicronHyderabad - Phoenix Aquila, India 3mo Leading verification of high-speed IPs (PCIe) and subsystems for memory and storage solutions, ensuring quality from architecture alignment through silicon bring-up.
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Career Accelerator Program - Mixed Signal Design Verification Engr Texas InstrumentsUnited States 3mo Developing verification plans, SystemVerilog test benches, and simulations for RTL and GLS to ensure first-pass silicon success for mixed-signal systems.
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New College Grad - HBM Analog Verification Engineer↗ Micron TechnologyTlaquepaque, JAL, MX 3mo Provide verification support for pre-silicon full chip designs and develop test benches for HBM and emerging memory architectures.
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Pre-Silicon Verification Engineer
AmazonHaifa, Haifa, Israel
3mo
Develop and execute comprehensive verification plans and test cases to validate hardware functionality and performance for semiconductor platforms.
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Principal DFT Engineer AnalogdevicesIndia, Bangalore, RMZ 3mo Architecting, implementing, and verifying advanced DFT solutions for complex digital ASICs and SoCs to ensure robust testability and manufacturing yield.
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CPU Design Verification Engineer IntelMalaysia, Penang 3mo Pre-silicon functional verification of CPU logic to ensure designs meet microarchitecture specifications.
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AMS Engineer OlixAustin, TX 3mo Senior Mixed-Signal Verification Engineer owning verification of analog and mixed-signal blocks for high-speed IO RX/TX chains in a new AI computing accelerator.
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Staff DFT Engineer Renesas-ElectronicsRemote 3mo Designing and implementing DFT architecture and test solutions for complex SoC/ASIC chips to ensure manufacturability and reliability.
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DFT Architect AlteraPenang 15, Penang, Malaysia 3mo Define and govern next-generation DFT architecture for advanced FPGA, SoC, and multi-die silicon platforms, ensuring world-class testability and manufacturability.
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Principal Verification Engineer ON SemiconductorMilan, Lombardia, Italy $66k–$66k3mo Developing comprehensive verification strategies and plans for power management integrated circuits to ensure functional and code coverage.
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Silicon Emulation Engineer WaymoMountain View (US-MTV-EMF690) $175k–$175k3mo Simulate future silicon designs and software on an emulation platform to enable functional and performance validation and left-shift of software development.
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