DFT Engineer (Design for Testability) - Staff
Core
Design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks, ensuring robust test coverage across wafer, die, stack, and system in package (SiP) test stages.
Role type
Staff DFT Design Engineer
Builds
Manufacturable, high quality HBM solutions
Domain
Semiconductor / Memory / High Bandwidth Memory (HBM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (DFT architectures, test access mechanisms)
Required skills
Digital design fundamentals, DFT concepts (scan, MBIST, boundary scan, JTAG), RTL design (SystemVerilog/VHDL), logic integration, semiconductor test flows
Preferred skills
HBM/DRAM/advanced memory product experience, TSV-based 3D integration knowledge, at-speed test/compression methodologies, DFT security/custom interfaces
Technologies
SystemVerilog, VHDL, JTAG, MBIST, TSV
Responsibilities
Define and implement HBM DFT architectures (scan, MBIST, JTAG, boundary scan, TSV test, redundancy, at-speed), Develop DFT solutions for base and DRAM die, Design and integrate test access mechanisms for wafer probe/cube/SiP flows, Collaborate with Product Engineering and Test Enablement to align DFT with manufacturing flows, Support yield learning, failure analysis, and debug, Work with logic/analog/layout/verification/physical design teams, Support silicon bring-up, debug, and qualification activities
Seniority
Staff, hands-on IC
