Staff Engineer - DV
Core
Hands-on development of high-performance CPU verification using System Verilog and UVM methodology.
Role type
Staff Engineer - Design Verification (DV)
Builds
Verification environments and test plans for RISC-V CPUs
Domain
Semiconductor / Chip Design / CPU Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, Object-Oriented Programming, CPU Architecture knowledge, Bus interface knowledge (AXI, PCIe), Test generation, Python scripting, Third-party VIP integration
Preferred skills
RISC-V specific experience
Technologies
System Verilog, UVM, Python, AXI, PCIe
Responsibilities
Write test cases and use test generators for targeted CPU verification scenarios; Collaborate with internal test generators to target coverage and test-plan scenarios; Integrate third-party verification IP (VIPs) into verification environments.
Seniority
Staff, hands-on IC
