Principal Design Engineer
Core
Lead digital verification strategy and architecture for semiconductor/ASIC/SoC projects, defining methodologies, testbenches, and execution plans.
Role type
Principal Design Engineer (Digital Verification)
Builds
Scalable verification environments, testbenches, and verification strategies for ASIC/SoC designs.
Domain
Semiconductor / ASIC / SoC / Digital Verification
Required skills
SystemVerilog, UVM, RTL design, timing analysis, coverage-driven verification, formal verification, bus protocols (AXI, AHB, PCIe, DDR), waveform analysis, low-power verification (UPF/CPF), constraint random testing
Preferred skills
Mentorship, cross-functional collaboration, project management
Technologies
Xcelium, VCS, Questa, Verisium, SimVision
Responsibilities
Define overall verification strategy and methodology; Design scalable verification environments including Bus Functional Models (BFMs), monitors, and scoreboards; Analyze specifications to identify critical features and corner cases; Lead customer interactions and convert requirements into DV execution plans; Write complex test cases and sequences; Lead root-cause analysis of design bugs; Implement constrained-random stimulus generation; Utilize formal tools to prove properties; Monitor and analyze coverage metrics; Oversee gate-level simulation (GLS); Provide final technical approval for verification phase; Mentor junior engineers on coding standards and debugging.
Seniority
Principal, strategy & mentorship