Principal Design Engineer
Core
Lead digital verification strategy and architecture for semiconductor/ASIC/SoC projects, defining methodologies, environments, and sign-off criteria.
Role type
Principal Design Engineer (Digital Verification)
Builds
Scalable verification environments, testbenches, and verification flows for ASIC/SoC chips.
Domain
Semiconductor / ASIC / SoC / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, RTL design, timing analysis, coverage-driven verification, formal verification, bus protocols (AXI, PCIe, DDR), waveform analysis, low-power verification (UPF/CPF), constraint random testing
Preferred skills
Mentorship, cross-functional collaboration, project management
Technologies
Xcelium, VCS, Questa, Verisium, SimVision
Responsibilities
Define overall verification strategy and infrastructure; Design scalable verification environments including BFMs, monitors, and scoreboards; Lead root-cause analysis of complex design bugs; Implement constrained-random stimulus generation; Oversee gate-level simulation and provide final technical approval for verification phase.
Seniority
Principal, hands-on IC with technical leadership
