AMS Engineer
Core
Senior Mixed-Signal Verification Engineer owning verification of analog and mixed-signal blocks for high-speed IO RX/TX chains in a new AI computing accelerator.
Role type
Senior IC mixed-signal verification engineer
Builds
Silicon-accurate simulation models, environments, and methodology for mixed-signal subsystems
Domain
Semiconductor hardware design, AI computing infrastructure, high-speed interconnect
Deliverable
production ML models
Required skills
Verilog-AMS, real-number modeling (SystemVerilog real/wreal), analog-digital co-simulation flows, SystemVerilog, assertion-based verification, analog behavioral modeling, transistor-level co-simulation setup, functional coverage definition, analog/digital boundary debugging
Preferred skills
High-speed SerDes/wireline architectures, calibration and adaptation loops, UVM/constrained-random verification, regression flow automation scripting, mixed-signal IP sign-off experience
Technologies
Spectre AMS, FastSpice, SystemVerilog, Python, TCL, Make
Responsibilities
Own verification strategy and test plan for mixed-signal subsystems; Define modeling approach and fidelity tiers; Develop and validate analog behavioral models; Build self-checking testbenches and reusable verification components; Drive AMS co-simulation flows; Define functional coverage and assertions for analog corner behavior; Debug and root-cause failures across analog/digital boundary; Partner with analog and DSP designers to review specs and translate intent into checkable models; Own block- and subsystem-level verification sign-off for tape-out; Build and maintain regression infrastructure and flow automation; Contribute to silicon bring-up and lab correlation
Seniority
Senior, hands-on IC