Staff Engineer
Core
Drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs, focusing on coherent data movement, protocol correctness, and subsystem integration.
Role type
Staff individual-contributor design verification engineer
Builds
Scalable cache-coherent interconnect subsystems for high-performance SoCs
Domain
Semiconductor chip design, interconnect protocols, system-on-chip (SoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, cache-coherent systems, on-chip interconnects, complex protocol behavior, testbench components, assertions, coverage models, debugging
Preferred skills
NoCs, memory fabrics, large subsystem integration, industry protocols (AXI, CHI, CXL, UCIe), formal verification, emulation/FPGA-assisted debug, Python scripting, mentoring
Technologies
SystemVerilog, UVM, Python, AXI, CHI, CXL, UCIe
Responsibilities
Own verification planning and execution for a scalable cache-coherent interconnect subsystem; Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models; Verify protocol adaptation and integration across multiple interface types; Drive verification of advanced interconnect behaviors such as QoS handling and arbitration policy; Define high-value directed and constrained-random test scenarios; Partner with architecture, design, formal, and software teams to clarify requirements and accelerate debug; Analyze failures efficiently and drive fixes across RTL and testbench infrastructure; Improve verification methodology and infrastructure for the broader interconnect verification effort.
Seniority
Staff, hands-on IC
