DFT Engineer (Design for Testability) - Staff
Core
Define, design, and integrate Design for Test (DFT) architectures for next-generation High Bandwidth Memory (HBM) products to ensure robust test coverage across wafer, die, stack, and system in package stages.
Role type
Staff DFT Design Engineer (Memory/Storage)
Builds
Manufacturable, high-quality HBM solutions
Domain
Semiconductor / Memory / Storage
Deliverable
production ML models | product features | infrastructure
Required skills
DFT concepts (scan, MBIST, boundary scan, JTAG), RTL design (SystemVerilog/VHDL), logic integration, semiconductor test flows, DRAM/ASIC design experience
Preferred skills
HBM/DRAM/advanced memory product experience, TSV-based 3D integration knowledge, at-speed test/compression methodologies, DFT security/custom interfaces
Technologies
SystemVerilog, VHDL, JTAG, MBIST, TSV
Responsibilities
Define and implement HBM DFT architectures including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures; Develop DFT solutions for base die and DRAM die considering stacked-die and cube-level test requirements; Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows; Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets; Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon; Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified; Collaborate with external partners and customers to align on custom DFT interfaces and security requirements; Support silicon bring-up, debug, and qualification activities including correlation between design intent and manufacturing test results.
Seniority
Staff, hands-on IC with strategic oversight
