Senior Principal Verification Engineer
Core
Ensuring functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
Role type
Senior Principal ASIC/SoC Verification Engineer
Builds
Production-ready SoC and IP designs validated for functional correctness, timing, and power constraints
Domain
Semiconductor hardware design and verification (ASIC/SoC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments, testbenches, coverage models)
Required skills
SystemVerilog (UVM/OVM), constrained-random verification, assertion-based verification, Gate-Level Simulation (GLS), power-aware verification (UPF/CPF), formal verification, Python/Perl/Tcl scripting, CI/CD automation
Preferred skills
Experience with EDA tools (Synopsys, Cadence, Siemens), knowledge of standard protocols (I2C, SPI, AXI), version control workflows
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, C++, Verilog, Synopsys, Cadence, Siemens, UPF, CPF, SDF
Responsibilities
Develop and execute SoC/IP-level verification plans aligned with design specifications; Architect and enhance SystemVerilog UVM/OVM-based testbenches; Perform Gate-Level Simulation (GLS) including timing verification and post-layout debug; Execute power-aware verification using UPF/CPF; Collaborate with design, architecture, and firmware teams to drive verification closure
Seniority
Senior, hands-on IC
