Lead/Principal DFT Engineer
Core
Designing and implementing Design for Test (DFT) architecture for large AI accelerator System-on-Chips (SoC) to enable high-speed inference and production testing.
Role type
Lead/Principal DFT Engineer
Builds
Large AI accelerator SoCs with embedded memory and complex logic
Domain
Semiconductor hardware design, AI accelerators, ASIC/SoC
Deliverable
production ML models | product features | infrastructure
Required skills
DFT architecture ownership, scan design, scan compression, ATPG (Automatic Test Pattern Generation), MBIST (Memory Built-In Self-Test), LBIST, boundary scan, EDA flow integration, hierarchical DFT for multi-core designs, memory test and repair strategies, power-aware testing, at-speed test strategies, RTL and physical design integration, silicon bring-up and debug, yield ramp management
Preferred skills
Mentorship of DFT engineers, strategic DFT planning, ambiguous problem solving
Technologies
Synopsys, Tessent
Responsibilities
Define DFT architecture, strategy, methodology, and signoff criteria; Drive integration of DFT tools into the EDA environment; Define hierarchical DFT, scan, compression, and ATPG approaches; Establish power-aware and at-speed test strategies; Collaborate with RTL and physical design teams for clean integration; Support production test and yield ramp with test engineering teams; Mentor DFT engineers
Seniority
Principal, hands-on IC with strategic ownership