Staff DFT Engineer
Core
Designing and implementing DFT architecture and test solutions for complex SoC/ASIC chips to ensure manufacturability and reliability.
Role type
Staff DFT Engineer (IC)
Builds
Production-ready SoC/ASIC chips with embedded DFT structures for automotive, industrial, and IoT markets.
Domain
Semiconductor design, Digital Logic, Test Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture design, Scan implementation (Stuck-At, At-Speed, Path-Delay), Scan compression, Boundary scan, MBIST, Low-Power DFT, Test coverage analysis, Timing constraint development, RTL design, ATPG test bench development, Pre/post-layout simulation
Technologies
UVM, Synopsys DFT tools, Cadence DFT tools, Verilog, SystemVerilog
Responsibilities
Create hierarchical DFT architectures for complex SoCs, Develop scan and MBIST test benches and simulation environments, Analyze test time and coverage for scan and MBIST patterns, Collaborate with test engineering teams to bring up production test programs, Implement various DFT structures including scan compression and boundary scan.
Seniority
Staff, hands-on IC
