Principal Hardware DFT Lead
Core
Architect, implement, and validate advanced DFT strategies for NXP's automotive-grade SoC products, ensuring high fault coverage and test efficiency from pre-tapeout to post-silicon.
Role type
Principal Hardware DFT Engineer
Builds
Automotive-grade System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Design / Automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan insertion and architecture, ATPG (Automatic Test Pattern Generation), Memory BIST (MBIST), Logic BIST (LBIST), Boundary Scan & JTAG, Test Compression, Verilog/SystemVerilog, Static Timing Analysis (STA), SDC constraints, Gate-level simulation (GLS), ATE data analysis, Tcl/Python/Perl scripting
Technologies
Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, Cadence Modus, Synopsys, Mentor Graphics, Cadence
Responsibilities
Define and implement advanced DFT strategies including Scan Architecture, JTAG, and BIST; Lead integration of digital subsystems and generate ATPG patterns; Drive post-silicon validation and debug activities; Coordinate with physical design and test engineering teams for timing closure.
Seniority
Principal, hands-on IC
